The HeiChips Summer School series is kindly supported by Heidelberg University, and BMFTR
HeiChips carries on the FPGA-Ignite Summer School series as we are now looking into microelectronics much beyond just FPGAs (which was a focus in the first three issues).HeiChips is a one week opportunity for networking, exciting lectures and a hackathon on designing a custom chip (that will be subsequently taped-out on the IHP 130nm BiCMOS Open Source PDK)
The HeiChips Summer School is kindly supported by Heidelberg University and BMFTR (the German Federal Ministry of Research, Technology and Space). Attending the event and all social activities is free of charge. However, participants have to arrange travel and accommodation on their own.
The free and open-source hardware (FOSH) community has achieved remarkable progress over just the last few years and we have now an ecosystem that is growing fast in ease-of-use, quality and features. HeiChips will address this with classes covering a wide spectrum of topics, including PDK design, analog and digital design but also pad-ring design and everything that is required for a successful tapeout.
Thanks to support from BMFTR (the German Federal Ministry of Research, Technology and Space) , HeiChips 2025 is free of charge to attend. (Attendees will have to arrange/pay travel and accommodation on their own.) The Central Hotel and the Ibis are in walking distance to the main train station and the venue and usually reasonably priced)
Please fill in the form in this link as soon as possible as the number of seats is limited.
Note that we review applications as they come in and we aim at a one-week turn-around time. Weaker applications will be pushed back and eventually admitted at a later date. The application process closes July 25th or if all seats are allocated. Therefore, early applications are suggested (in particular if you have to plan your travel in advance).HeiChips 2025 will take place in the European Institute for Neuromorphic Computing (EINC). Street address: Im Neuenheimer Feld 225a, 69120 Heidelberg
For public transport: leave at bus/tram stop Bunsengymnasium (Bus 31, 37; Tram 21, 24, 25). Google maps works reasonably well or install the VGN app on your phone.
It is usually best to directly book a hotel through a major portal. Hotel Central and the IBIS are close to the main train station and in walking distance to the campus.
Dirk Koch, Riadh Ben Abdelhamid Novel Computing Technologies, ZITI, Heidelberg University
Stefan Wallentowitz Stefan's home page, Hochschule München University of Applied Sciences
Prof. Dirk Koch
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
dirk.koch@ziti.uni-heidelberg.de
Dr. Riadh Ben Abdelhamid
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
riadh.benabdelhamid@ziti.uni-heidelberg.de
In this class you will get an introduction to LibreLane, its architecture and how to use it, as well as an overview of what a digital design flow looks like in general.
In this lab, you will get hands-on practice using LibreLane to design ASICs with an open source PDK
FPGA Ignite Summer School 2024, ZITI, Heidelberg University
FPGA Ignite Summer School 2023, ZITI, Heidelberg University
FPGA Ignite Summer School 2022, ZITI, Heidelberg University
Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Hasler has lived. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.
Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Hasler has lived. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.
Stefan Wallentowitz is a professor at Munich University of Applied Sciences. He holds a PhD in Electrical Engineering from Technische Universität München and an MBA from RWTH Aachen University. He is currently a member of RISC-V Board of Directors, a Director at the Free and Open Source Silicon Foundation, a Member of the Board of the Security Network Munich, a Advisor on “chip innovation” at TUM Venture Labs and a member of the Steering Committee of the RISC-V Summit Europe held in Munich in June 2024.
Stefan will talk about identifying candidates for ISA extensions and how to integrate those into the RISC-V ecosystem.
Krzysztof Herman - graduated from Wroclaw University of Science and Technology, Wroclaw, Poland completing his M.Sc in Acoustics and D.Sc. in Telecommunications engineering in 2007 and 2013 respectively. During early years of his research career worked at Wroclaw University of Science and Technology investigating air coupled ultrasound arrays and beamforming techniques and participated in two polar scientific expeditions to the Arctic and the Antarctic. In the period of 2015 to 2022 worked as a researcher and an academic teacher at the Department of Electrical and Electronics Engineering, University of the Bio-Bio, Concepcion, Chile. He considers himself to be one of the first "victims" of the open-source silicon movement, in which he got involved a few years ago. Currently works as a research associate at IHP Frankfurt (Oder) developing IHP’s open source PDK and handling open-source MPW submissions.
Leo Moser is an Open Source advocate and aspiring chip designer. He is currently finalizing his Master's degree at Graz University of Technology, where he designed Greyhound, a RISC-V SoC with tightly coupled FABulous eFPGA fabricated on IHP's SG13G2 process. Previously, Leo worked at Efabless, where he focused on PDK enablement for the IHP Open Source PDK and on analog automation with CACE. He is excited about the future of the free and open source silicon community.
Riadh is an Ex-Synopsys FPGA engineer on their flagship FPGA emulation system ZEBU. In 2017, he was a Japanese Government Scholarship (MEXT) recipient where he obtained his Master and PhD of Engineering in Computer Science from the University of Tsukuba in March 2020 and 2023 respectively. His research revolves around many-core processor architectures and overlays, High-Performance Computing and reconfigurable accelerators. He is also enthusiast about making his own many-core processor chip start-up. Riadh is currently a postdoctoral researcher at the Novel Computing Technologies Group at Heidelberg University, Germany, where he designed the SPARKLE architecture that was implemented on a VU9P FPGA with 1,024 RISC-V Barrel Processor cores and 16,384 interleaved Hardware Threads, delivering a peak 512,000 MIPS on a single FPGA device.
Dirk Koch is an expert in FPGA technology. His group maintains the FABulous open-source eFPGA framework and various other FPGA-related projects.
His class will briefly introduce the basic concepts of eFPGAs and the FABulous framework. We will then investigate the methods of using ISA subsetting, hardened custom instructions, reconfigurable custom instructions and software emulated instructions. We will also learn in particular how reconfigurable custom instructions can be made available in a CPU core. With this knowledge, we will run a lab where we will define a custom eFPGA eFPGA and implement custom instructions on that fabric using the open-source tools Yosys and nextpnr.