The HeiChips Summer School series is kindly supported by Heidelberg University, and BMFTR
HeiChips carries on the FPGA-Ignite Summer School series as we are now looking into microelectronics much beyond just FPGAs (which was a focus in the first three issues).HeiChips is a one-week opportunity for networking, exciting lectures and a hackathon on designing a custom chip (that will be subsequently taped-out on the IHP 130nm BiCMOS Open Source PDK)
The HeiChips Summer School is kindly supported by Heidelberg University and BMFTR (the German Federal Ministry of Research, Technology and Space). Attending the event and all social activities is free of charge. However, participants have to arrange travel and accommodation on their own.
The free and open-source hardware (FOSH) community has achieved remarkable progress over just the last few years and we have now an ecosystem that is growing fast in ease-of-use, quality and features. HeiChips will address this with classes covering a wide spectrum of topics, including PDK design, analog and digital design but also pad-ring design and everything that is required for a successful tapeout.
Thanks to support from BMFTR (the German Federal Ministry of Research, Technology and Space) , HeiChips 2025 is free of charge to attend. (Attendees will have to arrange/pay travel and accommodation on their own.) The Central Hotel and the Ibis are in walking distance to the main train station and the venue and usually reasonably priced)
Please fill in the form in this link as soon as possible as the number of seats is limited.
Note that we review applications as they come in and we aim at a one-week turn-around time. Weaker applications will be pushed back and eventually admitted at a later date. The application process closes July 25th or if all seats are allocated. Therefore, early applications are suggested (in particular if you have to plan your travel in advance).HeiChips 2025 will take place in the European Institute for Neuromorphic Computing (EINC). Street address: Im Neuenheimer Feld 225a, 69120 Heidelberg
For public transport: leave at bus/tram stop Bunsengymnasium (Bus 31, 37; Tram 21, 24, 25). Google maps works reasonably well or install the VGN app on your phone.
It is usually best to directly book a hotel through a major portal. Hotel Central and the IBIS are close to the main train station and in walking distance to the campus.
Dirk Koch, Riadh Ben Abdelhamid Novel Computing Technologies, ZITI, Heidelberg University
Stefan Wallentowitz Stefan's home page, Hochschule München University of Applied Sciences
Prof. Dirk Koch
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
dirk.koch@ziti.uni-heidelberg.de
Dr. Riadh Ben Abdelhamid
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
riadh.benabdelhamid@ziti.uni-heidelberg.de
While we will provide a virtual machine (or actually two) bundling all necessary tools, you can also install the tools natively. For this we recommend a Linux-based system. On Windows you can also use the Windows Subsystem for Linux (WSL). Some tools can also be run natively on Windows and MacOS, but make sure you have all tools in the same environment, since there can be dependencies between them. This list will be updated until HeiChip 2025 starts, so check for updates from time to time.
Quick Launch for Designers) on the IIC-OSIC-TOOLS
GitHub Repo:
Quickstart section of
the instructions, which uses the Scala CLI. Make sure to source
~/.profiles (depends on your platform, check the console output!)
after installing the Scala CLI (step 1).
-DCIRCT_SLANG_FRONTEND_ENABLED=ON .
Note: Make sure to get the commit "f1213ba8bdbcaba2a4903c5e078fb8c223a2ab39"
by simply updating the cloned repository using git pull
or cloning a fresh version of the repository, as this fixes an issue with
the CIRCT build.
| Poster Number | Poster Authors | Affiliation | Title | Abstract | |
|---|---|---|---|---|---|
| 1 | Pascal Gesell | Bern University of Applied Sciences | Ever wanted to design your own ASIC in VHDL? | This project investigates the implementation of a digital storage oscilloscope (DSO) on an application-specific integrated circuit (ASIC) using Tiny Tapeout. By employing modular design and open-source tools, it addresses challenges such as limited on chip memory and the specific constraints of ASIC design. The outcome demonstrates the feasibility of compact and functional ASIC development, integrating features like video output, external F-RAM buffering, and a test signal generator. | |
| 2 | Graeme M. Bragg, Jules Field | University of Southampton | Moodle & Verilator make open-source, web-based automated marking of SystemVerilog labs a reality | Moodle & Verilator make open-source, web-based automated marking of SystemVerilog labs a reality | |
| 3 | Marcin Kowalczyk | AGH University of Krakow | Processing event data from a neuromorphic vision sensor | Event cameras are neuromorphic sensors inspired by the human visual system. Due to the format of the vision data being sent, it is necessary to develop new algorithms and hardware archiectures to process it efficiently. | |
| 4 | Varun Posimsetty | Technical University of Munich | Low Cost Power Cycling Stimuli Generator for AMS Validation using an FPGA | A cost-effective, low-latency FPGA-based power cycling stimuli generator for post-silicon validation of analog mixed-signal devices. Traditional validation setups suffer from high equipment costs and switching delays. The proposed system replaces expensive multi-channel signal generators with a scalable FPGA solution capable of generating synchronized digital pulses and analog ramps. | |
| 5 | Spandan Das, Christoph Lueth, Tim Gueneysu, Pascal Sasdrich, Rolf Drechsler | University of Bremen and Ruhr University Bochum | EMBOSOM Emigrating Embedded Software Security into Modern Emerging Hardware Paradigms | Embedded systems are the basic building blocks of complex electronic devices and as such, their security must be guaranteed to ensure safety of the device itself. For such systems, it is very difficult to install additional software level security on top of the main program because of the space crunch. Hence our approach is to design a secure hardware along with an Instruction Set Architecture (ISA) such that the software becomes inherently secure in memory, even when designed using a fundamentally memory-unsafe programming language like C or C++. In order to achieve this, we are implementing a tagged memory along with an extended RISC-V ISA (an approach similar to CHERI) on an existing RISC-V Virtual Prototype, that can simulate the behavior of memory starved embedded systems. | |
| 6 | andrea.quirini, aisha.baloch, fabia.arshad, fabiola.colone, pierfrancesco.lombardo}@uniroma1.it | Ph.D researcher | Radar Frequency-Comparison Monopulse Validation Using FPGA-Generated Wideband Chirp Waveforms | Abstract: In this paper, we introduce a frequency-based Direction of Arrival (DoA) estimation technique for wideband radar systems employing Linear Frequency Modulated (LFM) signals. Conventional phase-comparison monopulse is subject to estimation ambiguities, especially in the case of a large baseline distance. In contrast, the proposed frequency-comparison monopulse leverages the time-to-frequency mapping property of LFM signals, enabling unambiguous DoA estimation for any antenna spacing. By leveraging a fully digital generation method for LFM signals implemented on the ZCU111 FPGA platform, we carry out an validation test of the frequency-comparison monopulse, demonstrating its effectiveness in addressing the limitations of conventional monopulse | |
| 7 | Gulafshan | Universtät Heidelberg | MemSim+: Realistic Behavioral Model for ReRAMs Capturing Non-Idealities | Memristors are promising candidates for in-memory computing systems, offering a potential solution to the von Neumann bottleneck in traditional computing architectures. Designing reliable and efficient memristive circuits re- quires accurate simulation models that can reflect real-world device behaviors, including their inherent non-idealities. In this talk, I will present MemSim+[1], a comprehensive behavioral model for memristors that captures both cycle-to- cycle (C2C) and device-to-device (D2D) variations in key parameters, such as high and low resistance states, threshold voltages, resistance drift, and switching dynamics. Unlike traditional models that rely on fixed values of key parameters [2,3,4,5,6], MemSim+ accounts for statistical distributions of these parameters—derived from extensive experimental data—to emulate real device variability. The model’s universality is validated using two types of memristors: SDC (Self-Directed Channel) and ECM (Electrochemical Metallization) devices. Electrical characterization was conducted on different SDC and ECM devices to capture D2D variability, while repeated measurements were performed on one device of corresponding technology to capture C2C variations. To more accurately emulate real-world non-idealities in memristor behavior, MemSim+ employs clipped Gaussian and multi-Gaussian approaches—going beyond the tra- ditional use of simple Gaussian distributions. These advanced statistical fitting techniques allow the exclusion of critical outlier ranges and provide a more accurate representation of key parameter variations. As a result, the Mem- Sim+ model captures the full spectrum of device variability more effectively, including memristance, resistance drift, threshold voltage, and switching dynamics. To demonstrate the impact of this variation-aware modeling, MemSim+ was used in circuit-level simulations of two stateful logics: IMPLY logic and FELIX-OR logic. The design constraints of these circuits depend on technological parameters as well as non-idealities of the memristor in that technology. Hence, a variation-aware circuit-technology co-design is crucial for maximizing the correct functionality of conceptual circuits. As the result, variation-aware circuit-technology co-design can significantly enhance the correctness probabilities of the IMPLY logic gate circuit, achieving correctness probability up to 88.75% (↑ 3.00%) for SDC technology and 85.75% (↑ 4.25%) for the ECM technology. Additionally, for the FELIX OR gate, the correctness probabilities increase to 85.75% (↑ 35.25%) for SDC technology and 84.00% (↑ 10.50%) for the ECM technology. The findings indicate that the typical simulation approach (using nominal values) leads to lower chances of the fabricated circuits functioning as expected. The results showcase the significance of circuit-technology co-design and their co-dependence, as well as the importance of considering non-idealities in the behavior of real devices when designing memristive circuits and systems. | |
| 8 | Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg Henkel | Karlsruhe Institute of Technology | Hardware/Software Co-Analysis for Worst Case Execution Time Bounds | We present a novel method for computing worst case execution time bounds without using a preexisting timing model. Instead, our method computes the WCET bound based on an instrumented hardware description of the target processor. This enables our method to automatically analyse a program's timing behavior in the presence of custom instruction set extensions. | |
| 9 | Emmanuel Innocent and Dr. O. O. Ilori | Obafemi Awolowo University, Ile-Ife Nigeria | A Highly Linear Wide Bandwidth Programmable Gain Amplifier in 0.18μm CMOS Process | Programmable Gain Amplifiers (PGAs) are fundamental to optimising signal dynamic range in systems such as medical electronic devices, telecommunications, and disk drives. In automatic gain control (AGC) systems, PGAs help maintain consistent signal levels under varying signal strengths, requiring a wide dB-in-linear gain range. However, modern analogue front-ends demand not only wide gain control but also high bandwidth, low power consumption, compact area, and good noise performance. This project presents the design of a CMOS PGA targeting a gain range of –12 dB to 20 dB, bandwidth of 100–500 MHz, distortion ≤ –55 dB, and power consumption ≤ 25 mW. The initial implementation uses an operational transconductance amplifier (OTA) with series and feedback switch-resistor networks. Both conventional folded cascode (FC) and recycling folded cascode (RFC) amplifiers were explored. While the RFC provided improved open-loop gain and gain-bandwidth product over the FC, the closed-loop bandwidth remained limited to 1–2 MHz — far below the target. The current implementation achieved a figure of merit (FoM) of 1187 MHz·pF/mA, and closed-loop bandwidth was extended by a factor of 100 due to feedback. However, redesign is needed to meet the bandwidth requirement. Future work proposes a current operational amplifier based on the second-generation current conveyor (CCII), leveraging current-mode techniques to achieve high speed and low power operation. This approach, when implemented with high-speed IHP BiCMOS technology, is expected to meet the performance targets for wideband, low-power PGAs in modern systems. | |
| 10 | Jan Zielasko, Rolf Drechsler | Institute of Computer Science, University of Bremen, Germany Cyber-Physical Systems, DFKI GmbH, Germany |
Optimizing Hardware for Neural Network Inference using Virtual Prototypes | This poster shows how virtual prototypes can be used as an analysis platform to identify suitable application specific hardware optimizations. | |
| 11 | Jonas Bühler, Arun Ashok, Lammert Duipmans, Christian Grewing, Dennis Nielinger, Patrick Vliex, André Zambanini, and Stefan Van Waasen | Institute for Integrated Computing Architectures (ICA) – PGI-4, Forschungszentrum Jülich GmbH, Germany | TOWARDS SCALABLE READOUT IC‘S FOR SEMICONDUCTOR QUANTUM DOTS | Universal quantum computing requires a scalable system with millions of qubits. Realizing fast, high-fidelity readout remains a central bottleneck, particularly when striving for scalable architectures that minimize spatial overhead, wiring density, and energy consumption. To address these limitations, we present our activities on development of integrated circuits at cryogenic temperatures. Especially an integrated readout circuitry implemented in a 22 nm FD-SOI technology. This IC will be connected to a Single Electron Transistor (SET). The prototype is made for reading out two SETs. It implements a high-speed mode for single-bit readout, enabling rapid discrimination between the│0〉and │1〉state, as well as a high-resolution mode for tuning, which amplifies the signal and passes it to the room-temperature electronics. We characterize this IC inside a closed cycle Gifford-McMahon cryostat at a temperature of 6 K. The measurement shows a power consumption of 33.6 μW/SET for the single-bit readout and 216 μW for the high-resolution mode. With the correlated double sampling with times of 2×1 μs, the circuit shows low noise of 223 pA (1σ) for single-bit readout, while the high-resolution mode has an input-referred noise level of 188 pA RMS (10 Hz to 1 MHz). The IC advances scalable, integrated readout solutions and marks a critical milestone on the path toward universal quantum computing | |
| 12 | Luis E. Ardila-Perez, Lukas Scheller | Karlsruhe Institute of Technology (KIT) | SCALLOP: A Scalable CryoCMOS DAC Array in IHP 130nm BiCMOS for Flux-Bias Control of Superconducting Qubits | Superconducting qubits are one of the most promising technologies for building large-scale quantum computers. However, scaling these systems from a few qubits to thousands or more requires a fundamental rethinking of how we control them, especially when it comes to delivering precise magnetic flux to each qubit. Today, this is typically done using room-temperature DACs that generate analog signals routed through long, lossy cables into the cryostat. This approach is not scalable. The flux DACs quickly become the limiting factor, consuming too much power, space, and wiring bandwidth as the qubit count increases. SCALLOP focuses on solving this problem first, by designing low-power, high-precision DACs and associated sequencer logic that operate directly at cryogenic temperatures (~4K), close to the qubits themselves. To make this possible, SCALLOP uses a fully open-source ASIC design flow, making the development transparent, collaborative, and accessible. These DACs are being developed using the new cryo-compatible PDK from IHP, a BiCMOS process specially tailored for operation at low temperatures and high frequencies, ideal for integration with superconducting qubit systems. | |
| 13 | Philippos Papaphilippou | University of Southampton | Reconfigurable processing units inside RISC-V cores | This poster discusses the possibility to integrate small FPGAs inside CPU cores. A general purpose architecture that includes FPGAs has already been introduced to combine the advantages of FPGAs and CPUs, such as flexibility and easy development. The goal is to increase the homogeneity of eFPGA-based solutions within the rest of the core architecture, such as for RISC-V cores, so that the remainder of the micro-architecture evolves in unison with the added reconfigurability. Ongoing research investigates how to best "connect" the two technologies, with the help of the increasingly open nature of RISC-V and eFPGAs. | |
| 14 | Hossam O. Ahmed | The American University of the Middle East (AUM) | Unpredictable by Design: Race Hazard & Jitter-Enhanced TRNG with Braided Logic Gates on FPGA | Security in the modern digital era critically depends on robust cryptographic mechanisms, which require high-quality sources of randomness. This work presents a novel True Random Number Generator (TRNG) architecture called the Braided and Hybrid Cross-Coupled Entropy Source (B+HCCES) TRNG. The design exploits race hazards and jitter in braided and cross-coupled logic gates, and is implemented in VHDL on an Intel Cyclone V FPGA. The B+HCCES module operates at a 300 MHz sampling frequency using an embedded phase-locked loop, and achieves a throughput that is 3.33 times greater than leading state-of-the-art TRNGs, while maintaining a compact hardware footprint. Experimental results demonstrate that the generated random sequence passes both the NIST SP800-90B and BSI AIS-31 test suites, confirming the reliability and quality of the B+HCCES TRNG for cryptographic and security applications. | |
| 15 | Kevin Klein | Heidelberg University | FPGA Ray Marching: 3D CORDIC for Extreme Mandelbulb Precision | Ray marching is a widely adopted technique for rendering complex 3D structures. However traditional GPU implementations suffer from precision limitations at exceptionally deep zoom levels. In this paper, we introduce a novel high-precision ray marching technique that leverages a 3D Coordinate Rotation Digital Computer (CORDIC) core. This approach is the first of its kind to incorporate a 3D CORDIC core for ray marching and it demonstrates that CORDIC can enable extreme high-precision rendering of 3D fractals. Implementing this method on an FPGA platform permits significantly deeper zoom levels and more intricate 3D fractal visualizations. |
FPGA Ignite Summer School 2024, ZITI, Heidelberg University
FPGA Ignite Summer School 2023, ZITI, Heidelberg University
FPGA Ignite Summer School 2022, ZITI, Heidelberg University
Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Hasler has lived. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.
This talk will delve into our startup journey at Sensesemi, where we developed a handheld body vital monitoring system. I will share insights on my experience and challenges of a startup, navigating the realities of productization. Additionally, I plan to discuss the potential of AI-driven chip design and RISC-V-based customization for future applications, particularly in healthcare and automotive systems.
Jennifer Hasler received her B.S.E. and M.S. degrees in electrical engineering from Arizona State University in August 1991. She received her Ph.D. in computation and neural systems from California Institute of Technology in February 1997. Hasler is a professor at the Georgia Institute of Technology in the School of Electrical and Computer Engineering; Atlanta is the coldest climate in which Hasler has lived. Hasler founded the Integrated Computational Electronics (ICE) laboratory at Georgia Tech, a laboratory affiliated with the Laboratories for Neural Engineering. Hasler is a member of Tau Beta P, Eta Kappa Nu, and the IEEE.
Stefan Wallentowitz is a professor at Munich University of Applied Sciences. He holds a PhD in Electrical Engineering from Technische Universität München and an MBA from RWTH Aachen University. He is currently a member of RISC-V Board of Directors, a Director at the Free and Open Source Silicon Foundation, a Member of the Board of the Security Network Munich, a Advisor on “chip innovation” at TUM Venture Labs and a member of the Steering Committee of the RISC-V Summit Europe held in Munich in June 2024.
Stefan will talk about identifying candidates for ISA extensions and how to integrate those into the RISC-V ecosystem.
Krzysztof Herman - graduated from Wroclaw University of Science and Technology, Wroclaw, Poland completing his M.Sc in Acoustics and D.Sc. in Telecommunications engineering in 2007 and 2013 respectively. During early years of his research career worked at Wroclaw University of Science and Technology investigating air coupled ultrasound arrays and beamforming techniques and participated in two polar scientific expeditions to the Arctic and the Antarctic. In the period of 2015 to 2022 worked as a researcher and an academic teacher at the Department of Electrical and Electronics Engineering, University of the Bio-Bio, Concepcion, Chile. He considers himself to be one of the first "victims" of the open-source silicon movement, in which he got involved a few years ago. Currently works as a research associate at IHP Frankfurt (Oder) developing IHP’s open source PDK and handling open-source MPW submissions.
Leo Moser is an open source silicon advocate and aspiring chip designer. He obtained his Master's degree at Graz University of Technology, majoring in microelectonics and IC design. In his work, he designed Greyhound, a RISC-V SoC with tightly coupled FABulous eFPGA fabricated on IHP's SG13G2 process. Previously, Leo worked at Efabless, where he focused on PDK enablement for the IHP Open Source PDK and on analog automation with CACE. He is excited about the future of the free and open source silicon community.
Riadh is an Ex-Synopsys FPGA engineer on their flagship FPGA emulation system ZEBU. In 2017, he was a Japanese Government Scholarship (MEXT) recipient where he obtained his Master and PhD of Engineering in Computer Science from the University of Tsukuba in March 2020 and 2023 respectively. His research revolves around many-core processor architectures and overlays, High-Performance Computing and reconfigurable accelerators. He is also enthusiast about making his own many-core processor chip start-up. Riadh is currently a postdoctoral researcher at the Novel Computing Technologies Group at Heidelberg University, Germany, where he designed the SPARKLE architecture that was implemented on a VU9P FPGA with 1,024 RISC-V Barrel Processor cores and 16,384 interleaved Hardware Threads, delivering a peak 512,000 MIPS on a single FPGA device.
Dr. Veena S. Chakravarthi is a Bangalore-based technologist, SoC architect, and educator with three decades of impactful experience. She has been pivotal in establishing numerous VLSI Design & Incubation centers and leading high-performance global technology teams at companies like ITI Limited, Mindtree Consulting, and Synopsys, where she developed and led the "Purple Certification" program, training 1000 employees. As a co-founder of Sensesemi Technologies, she also ventured into healthcare innovation. Academically, Dr. Chakravarthi served as Research Head and Adjunct Professor in ECE, guiding 5 PhD scholars. She holds a PhD in Low Power VLSI Design and an Executive Management certification from IIM Bangalore. An inventor and author, she has filed seven patents (four granted) in VLSI and Healthcare and authored six VLSI books with Springer Nature, which has seen cumulative one lakh downloads. A Senior IEEE Member, she currently serves as Director at LeadSOC Technologies, spearheading an Offshore Development Center for US-based AI startup, Cognichip.ai.
Dirk Koch is an expert in FPGA technology. His group maintains the FABulous open-source eFPGA framework and various other FPGA-related projects.
His class will briefly introduce the basic concepts of eFPGAs and the FABulous framework. We will then investigate the methods of using ISA subsetting, hardened custom instructions, reconfigurable custom instructions and software emulated instructions. We will also learn in particular how reconfigurable custom instructions can be made available in a CPU core. With this knowledge, we will run a lab where we will define a custom eFPGA eFPGA and implement custom instructions on that fabric using the open-source tools Yosys and nextpnr.