Summer School on Open-Source Chip Design
August 3 – 7, 2026 · Heidelberg, Germany
One week of lectures, hands-on workshops, and a hackathon — design your own chip and tape it out on the IHP 130nm Open Source PDK.
The HeiChips Summer School series is kindly supported by Heidelberg University, BMFTR and Chipdesign Germany.
HeiChips carries on the FPGA-Ignite Summer School series as we are now looking into microelectronics much beyond just FPGAs (which was a focus in the first three issues).
HeiChips is a one-week opportunity for networking, exciting lectures and a hackathon on designing a custom chip (that will be subsequently taped-out on the IHP 130nm CMOS5L Open Source PDK)
The HeiChips Summer School is kindly supported by Heidelberg University, BMFTR and Chipdesign Germany. Attending the event and all social activities is free of charge. However, participants have to arrange travel and accommodation on their own.
The free and open-source hardware (FOSH) community has achieved remarkable progress over just the last few years and we have now an ecosystem that is growing fast in ease-of-use, quality and features. HeiChips will address this with classes covering a wide spectrum of topics, including PDK design, analog and digital design but also pad-ring design and everything that is required for a successful tapeout.
Thanks to support from BMFTR, HeiChips 2026 is free of charge to attend. (Attendees will have to arrange/pay travel and accommodation on their own.) The Central Hotel and the Ibis are in walking distance to the main train station and the venue and usually reasonably priced)
While HeiChips is free of charge, we invite participants from industry or participants in a more senior role to help financing HeiCHips by registering here. You can add your registration fee and a recommended figure for attending the whole week is 300 Euro.
Please fill in the form in this link as soon as possible as the number of seats is limited.
Note that we review applications as they come in and we aim at a one-week turn-around time. Weaker applications will be pushed back and eventually admitted at a later date. The application process closes July 25th or if all seats are allocated. Therefore, early applications are suggested (in particular if you have to plan your travel in advance).HeiChips 2026 will take place in the European Institute for Neuromorphic Computing (EINC). Street address: Im Neuenheimer Feld 225a, 69120 Heidelberg
For public transport: leave at bus/tram stop Bunsengymnasium (Bus 31, 37; Tram 21, 24, 25). Google maps works reasonably well or install the VRN app on your phone.
It is usually best to directly book a hotel through a major portal. Hotel Central and the IBIS are close to the main train station and in walking distance to the campus.
Dirk Koch, Riadh Ben Abdelhamid Novel
Computing Technologies, ZITI, Heidelberg University
Prof. Dirk Koch
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
dirk.koch@ziti.uni-heidelberg.de
Dr. Riadh Ben Abdelhamid
Novel Computing Technologies
Universität Heidelberg
Institut für Technische Informatik (ZITI)
Im Neuenheimer Feld 368, 69120 Heidelberg
riadh.benabdelhamid@ziti.uni-heidelberg.de
Riadh is an Ex-Synopsys FPGA engineer on their flagship FPGA emulation system ZEBU. In 2017, he was a Japanese Government Scholarship (MEXT) recipient where he obtained his Master and PhD of Engineering in Computer Science from the University of Tsukuba in March 2020 and 2023 respectively. His research revolves around many-core processor architectures and overlays, High-Performance Computing and reconfigurable accelerators. He is also enthusiast about making his own many-core processor chip start-up. Riadh is currently a postdoctoral researcher at the Novel Computing Technologies Group at Heidelberg University, Germany, where he designed the SPARKLE architecture that was implemented on a VU9P FPGA with 1,024 RISC-V Barrel Processor cores and 16,384 interleaved Hardware Threads, delivering a peak 512,000 MIPS on a single FPGA device.
Simon Dorrer is an internationally recognized electronics expert and researcher at the Institute of Signal Processing (ISP) at Johannes Kepler University (JKU) Linz. Having graduated with distinction in Electronics and Information Technology (specializing in IC design, DSP, and RF technology), his work bridges the gap between analog-mixed-signal circuit design and cutting-edge microelectronics. Alongside his academic career, he serves as the official "Electronics Expert" for SkillsAustria, where he designs national competition projects and trains the next generation of top-tier electronics talents for EuroSkills and WorldSkills.
Georg spent a long time designing digital circuits in Verilog. He got his degrees from TU Ilmenau in collaboration with IMMS Institute for Microelectronics and Mechatronics Systems where took over the digital design team and is currently the team lead for design methodology. He focuses on new (and obviously open source) tools for making the design and synthesis process more efficient and (sometimes) more user friendly.
Dirk Koch is an expert in FPGA technology. His group maintains the FABulous open-source eFPGA framework and various other FPGA-related projects.
His class will briefly introduce the basic concepts of eFPGAs and the FABulous framework. We will then investigate the methods of using ISA subsetting, hardened custom instructions, reconfigurable custom instructions and software emulated instructions. We will also learn in particular how reconfigurable custom instructions can be made available in a CPU core. With this knowledge, we will run a lab where we will define a custom eFPGA eFPGA and implement custom instructions on that fabric using the open-source tools Yosys and nextpnr.
Matthias Köfferlein is a veteran Software Engineer with more than 25 years of experience in the semiconductor and EDA industries. He has held senior engineering positions at industry giants like Carl Zeiss, Qimonda, and Infineon. Matthias is internationally renowned as the creator of KLayout, a flagship open-source tool utilized worldwide for integrated circuit design and layout manipulation. As an experienced industry expert and lecturer, he bridges the gap between hardware and software engineering, making him a premier mentor for students exploring modern microelectronics and automated layout design.
Caren Kresse is the Managing Director and a Board Member at OSADL (Open Source Automation Development Lab eG). With an extensive background in open-source compliance and technology, she spearheads critical industry initiatives including the OSADL Open Source Policy project, the License Obligations Checklists, and the OSSelot curation database. As an experienced speaker and educator, Caren regularly advises industrial companies on how to navigate the complex legal and technological landscapes of FOSS, from open-innovation architectures to upcoming regulatory shifts like the Cyber Resilience Act.
Leo Moser is an advocate of free and open-source silicon (FOSSi) and aspiring chip designer. He is part of the FABulous team and is also currently involved with wafer.space. Leo received his Master's degree from Graz University of Technology, where he designed Greyhound: a RISC-V SoC with tightly coupled FABulous eFPGA fabricated on IHP's SG13G2 process. Previously, Leo worked at Efabless, where he focused on PDK enablement for the IHP Open Source PDK and on analog automation with CACE. He is excited about the future of the free and open-source silicon community.
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